/////////////////
//行為模式
/////////////////
module top
integer ia,ib;
reg a,b;
wire out;
and_behavioral and1(out,a,b);
initial
begin
for (ia=0; ia<=1; ia = ia+1)
begin
a = ia;
for (ib=0; ib<=1; ib = ib + 1)
begin
b = ib;
#1 $display("a=%d b=%d out=%d",a,b,out);
end
end
end
endmodule
module and_behavioral(out,a,b);
input a,b;
output out;
wire a,b;
reg out;
always @(a or b)
out = a & b;
endmodule
/////////////////
//結構模式
/////////////////
module top;
wire A, B, OUT
system_clock #400 clock1(A);
system_clock #200 clock2(B);
and a1(OUT, A, B);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial clk=0;
always
begin
#(PERIOD/2) clk=~clk;
end
always@(posedge clk)
if($time>1000)$stop;
endmodule
