1位元半加法器設計 採用 UDP

module top();
wire a,b,c,s;

system_clock #100 clock1(a);
system_clock #50 clock1(b);

Adder_Sum S1(s, a, b);
Adder_Carry C1(c, a, b);

endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

primitive Adder_Sum(Sum, InA, InB);
output Sum;
input InA, InB;

table
// inputs : output
00 : 0;
01 : 1;
10 : 1;
11 : 0;
endtable
endprimitive

primitive Adder_Carry(Carry, InA, InB);
output Carry;
input InA, InB;
table
// inputs : output
00 : 0;
01 : 0;
10 : 0;
11 : 1;
endtable
endprimitive