module top;
reg [1:0] A, B;
reg Cin;
wire[1:0] Sum;
adder2 M2(Cout, Sum, A, B, Cin);
initial
begin
A=2'd1;
B=2'd1;
Cin=1'd1;
end
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;
adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);
endmodule
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